Vhdl Binary To Integer Converter Boxes
Library
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Utility Blocks
Description
The Integer to Bit Converter block maps each integer (or fixed-point value) in the input vector to a group of bits in the output vector.
The block maps each integer value (or stored integer when you use a fixed point input) to a group of M bits, using the selection for the Output bit order to determine the most significant bit. The resulting output vector length is M times the input vector length.
When you set the Number of bits per integer parameter to M and Treat input values as to Unsigned, then the input values must be between 0 and 2M-1. When you set Number of bits per integer to M and Treat input values as to Signed, then the input values must be between –2M-1 and 2M-1-1. During simulation, the block performs a run-time check and issues an error if any input value is outside of the appropriate range. When the block generates code, it does not perform this run-time check.
This block is single-rate and single-channel. It accepts a length N column vector or a scalar-valued (N = 1) input signal and outputs a length N·M column vector.
The block can accept the data types int8, uint8, int16, uint16, int32, uint32, single, double, and fixed point.
Dialog Box
The number of bits the block uses to represent each integer of the input. This parameter must be an integer between 1 and 32.
Indicate if the integer value input ranges should be treated as signed or unsigned. The default setting is Unsigned.
Define whether the first bit of the output signal is the most significant bit (MSB) or the least significant bit (LSB). The default selection is MSB first.
You can choose the following Output data type options:
Inherit via internal ruleSmallest integerSame as inputdoublesingleuint8uint16uint32
The default selection for this parameter is Inherit via internal rule.
When the parameter is set to Inherit via internal rule, the block determines the output data type based on the input data type.
If the input signal is floating-point (either
singleordouble), the output data type is the same as the input data type.If the input data type is not floating-point, the output data type is determined as if the parameter is set to
Smallest integer.
When the parameter is set to Smallest integer, the block selects the output data type based on settings used in the Hardware Implementation Pane (Simulink) of the Configuration Parameters dialog box.
If you select ASIC/FPGA, the output data type is the ideal one-bit size; ufix1.
For all other selections, the output data type is an unsigned integer with the smallest available word length, as defined in the Hardware Implementation settings (e.g. uint8)
Examples
Fixed-Point Integer To Bit and Bit To Integer Conversion (Audio Scrambling and Descrambling Example)
Overview
This example illustrates how to use the Bit to Integer and Integer to Bit Converter blocks with fixed-point signals.
This example uses a simplified audio scrambler configuration and a 16-bit, fixed-point digital audio source, which is recorded speech. The left-side of the model represents the audio scrambler subsystem and the right-side represents the descrambler subsystem.
Opening the Model
You can open the model by typing doc_audioscrambler at the MATLAB® command line.
Structure
In the audio scrambler subsystem, the Integer to Bit Converter block unpacks each 16-bit audio sample into a binary, 1-bit signal. The binary signal passes to a linear feedback shift register (LFSR) scrambler, which randomizes the bits in a controllable way, thereby scrambling the signal. The Communications Toolbox™ Scrambler block is used in the LFSR implementation. From the LFSR, the scrambled audio bits pass to the Bit to Integer Converter block. This block packs the scrambled 1-bit samples into 16-bit audio samples. The audio samples pass to the Data Type Conversion block, which converts the integer-based audio samples back into fixed-point samples.
The fixed-point samples pass from the scrambler subsystem to a channel. The channel sends the samples to the descrambler subsystem. For illustrative purposes, this example uses a noiseless channel. In an actual system, a channel may introduce noise. Removing such noise requires a more sophisticated design.
In the audio descrambler subsystem, the Integer to Bit Converter block unpacks each 16-bit audio sample into a binary, 1-bit signal. The binary signal passes to a linear feedback shift register (LFSR) descrambler, which randomizes the bits in a controllable way, reversing the scrambling process. This LFSR descrambler implementation uses the Communications Toolbox Descrambler block. From the LFSR, the descrambled audio bits pass to the Bit to Integer Converter block. This block packs the descrambled 1-bit samples into 16-bit audio samples. The audio samples pass to the Data Type Conversion block, which converts the integer-based audio samples back into fixed-point samples.
In Simulink, the sfix16_En15 data type represents a signed (s) fixed-point (fix) signal with word length 16 and fraction length 15. Therefore, this model represents audio signals using the sfix16_En15 data type, except when converting to and from 1-bit binary signals. All 1-bit signals are represented by ufix1, as seen at the output of the Integer to Bit Converter block. The audio source has a frame size (or number of samples per frame) of 1024. For more information on fixed-point signals, please refer to Fixed-Point Numbers in the Simulink documentation.
Running the Model
You must run the example before you can listen to any of the audio signals.
You can run the example by clicking Simulation > Run.
You can hear the audio signals by clicking the model’s yellow, audio icons.
Converter Block Settings
In the audio scrambler and descrambler subsystems, the Integer to Bit Converter block settings are:
Number of bits per integer:
16Treat input values as:
SignedMilioner za decu.Output bit order:
MSB firstOutput data type:
Inherit via internal rule
In the audio scrambler and descrambler subsystems, the Bit to Integer Converter block settings are:
Number of bits per integer:
16Input bit order:
MSB firstAfter bit packing, treat resulting integer values as:
SignedOutput data type:
Inherit via internal rule
Extended Capabilities
C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.
See Also
Blocks
Functions
de2bidec2bin
Using both Numeric_Std and Std_Logic_Arith Package Files
Below are the most common conversions used in VHDL. The page is broken up into two sections. The first half of the page shows conversions using the Numeric_Std package file. The second half of the page shows conversions using the Std_Logic_Arith package file. It is good practice to use the Numeric_Std package as you should not use Std_Logic_Arith. Since many people still insist on using it, both examples are demonstrated below.
Note that many of the below examples use the 'lengthVHDL attribute. This attribute makes your code more portable and versatile, so it should be used.
Example Conversions using Numeric Std
Example Conversions using Std_Logic_Arith
Convert from Integer to Signed using Numeric_Std
The below example uses the to_signed conversion, which requires two input parameters. The first is the signal that you want to convert, the second is the length of the resulting vector.
Convert from Integer to Std_Logic_Vector using Numeric_Std
First you need to think about the range of values stored in your integer. Can your integer be positive and negative? If so, you will need to use the to_signed() conversion. If your integer is only positive, you will need to use the to_unsigned() conversion.
Both of these conversion functions require two input parameters. The first is the signal that you want to convert, the second is the length of the resulting vector.
Convert from Integer to Unsigned using Numeric_Std
The below example uses the to_unsigned conversion, which requires two input parameters. The first is the signal that you want to convert, the second is the length of the resulting vector.
Convert from Std_Logic_Vector to Integer using Numeric_Std
First you need to think about the data that is represented by your std_logic_vector. Is it signed data or is it unsigned data? Signed data means that your std_logic_vector can be a positive or negative number. Unsigned data means that your std_logic_vector is only a positive number. The example below uses the unsigned() typecast, but if your data can be negative you need to use the signed() typecast. Once you cast your input std_logic_vector as unsigned or signed, then you can convert it to integer as shown below:
Convert from Std_Logic_Vector to Signed using Numeric_Std
This is an easy conversion, all you need to do is cast the std_logic_vector as signed as shown below:
Convert from Std_Logic_Vector to Unsigned using Numeric_Std
This is an easy conversion, all you need to do is cast the std_logic_vector as unsigned as shown below:
Convert from Signed to Integer using Numeric_Std
This is an easy conversion, all you need to do is use the to_integer function call from numeric_std as shown below:
Convert from Signed to Std_Logic_Vector using Numeric_Std
This is an easy conversion, all you need to do is use the std_logic_vector cast as shown below:
Convert from Signed to Unsigned using Numeric_Std
This is an easy conversion, all you need to do is use the unsigned cast as shown below:
Convert from Unsigned to Integer using Numeric_Std
This is an easy conversion, all you need to do is use the to_integer function call from numeric_std as shown below:
Convert from Unsigned to Signed using Numeric_Std
This is an easy conversion, all you need to do is use the signed cast as shown below:
Convert from Unsigned to Std_Logic_Vector using Numeric_Std
This is an easy conversion, all you need to do is use the std_logic_vector cast as shown below:
Convert from Integer to Signed using Std_Logic_Arith
The below example uses the conv_signed conversion, which requires two input parameters. The first is the signal that you want to convert, the second is the length of the resulting vector.
Convert from Integer to Std_Logic_Vector using Std_Logic_Arith
The below example uses the conv_std_logic_vector conversion, which requires two input parameters. The first is the signal that you want to convert, the second is the length of the resulting vector.
One thing to note here is that if you input a negative number into this conversion, then your output std_logic_vector will be represented in 2's complement signed notation.
Convert from Integer to Unsigned using Std_Logic_Arith
The below example uses the conv_unsigned conversion, which requires two input parameters. The first is the signal that you want to convert, the second is the length of the resulting vector.
Convert from Std_Logic_Vector to Integer using Std_Logic_Arith
First you need to think about the data that is represented by your std_logic_vector. Is it signed data or is it unsigned data? Signed data means that your std_logic_vector can be a positive or negative number. Unsigned data means that your std_logic_vector is only a positive number. The example below uses the unsigned() typecast, but if your data can be negative you need to use the signed() typecast. Once your input std_logic_vector is unsigned or signed, then you can convert it to integer as shown below:
Convert from Std_Logic_Vector to Signed using Std_Logic_Arith
This is an easy conversion, all you need to do is cast the std_logic_vector as signed as shown below:
Convert from Std_Logic_Vector to Unsigned using Std_Logic_Arith
This is an easy conversion, all you need to do is cast the std_logic_vector as unsigned as shown below:
Convert from Signed to Integer using Std_Logic_Arith
This is an easy conversion, all you need to do is use the conv_integer function call from std_logic_arith as shown below:
Convert from Signed to Std_Logic_Vector using Std_Logic_Arith
This is an easy conversion, all you need to do is use the std_logic_vector cast as shown below:
Convert from Signed to Unsigned using Std_Logic_Arith
This is an easy conversion, all you need to do is use the unsigned cast as shown below:
Convert from Unsigned to Integer using Std_Logic_Arith
This is an easy conversion, all you need to do is use the conv_integer function call from std_logic_arith as shown below:
Convert from Unsigned to Signed using Std_Logic_Arith
This is an easy conversion, all you need to do is use the signed cast as shown below:
Convert from Unsigned to Std_Logic_Vector using Std_Logic_Arith
This is an easy conversion, all you need to do is use the std_logic_vector typecast as shown below:
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